1. Field of the Invention
The present invention relates to a substrate structure of a semiconductor device having vertical power MISFETs (Metal Insulator Field Effect Transistors) each having a gate electrode formed on a semiconductor substrate, as well as a method of manufacturing this substrate structure.
2. Description of the Related Art
In a vertical power MIS (including a MOS (Metal Oxide Semiconductor) FET formed on a semiconductor substrate, a drain current flows between a source and drain electrodes formed on a top and bottom surfaces, respectively, of a semiconductor substrate. Such an element allows the resistance of a current passage to be reduced and is thus often used as a power device.
FIG. 34 shows the sectional structure of a super junction type MISFET currently put to practical use. A semiconductor substrate 100 is composed of a first semiconductor substrate and a second semiconductor substrate consisting of an epitaxial growth layer. The first semiconductor substrate, which functions as an N+ drain area 101, contacts with a drain electrode 105. The second semiconductor substrate, which functions as N− drain areas 102, is provided with first P base areas 103.
Second P base areas 106, which contact with the first P base areas 103, are formed under a surface of the second semiconductor substrate. Reference numerals 107, 108, 109, and 110 denote an N source area, a gate insulating film, a gate area, and a source area.
The width of the P base area 103 and the N− drain area 102 located between the P base areas 103 (a P and N type pillar layers, respectively) and the amounts of P and N type impurities contained in these areas are optimally designed. Thus, if a reverse bias voltage is applied to the MISFET, the P and N type pillar layers are depleted. This structure enables on resistance to be reduced compared to other vertical MISFETs.
Other known examples of a MISFET improved so as to reduce the on resistance is described in U.S. Pat. No. 5,216,275 and Jpn. Pat. Appln. KOKAI Publication No. 2000-40822. In This U.S. Patent pillar-like P-type areas (corresponding to 103 in FIG. 34 of the specification) connected to base areas are formed of trenches as shown in FIG. 2 or the like. However, this patent does not clearly state that it can completely deplete the pillar layers and reduce the on resistance. Further, the latter publication describes the formation of both P and N layers in a drift layer by diffusion. However, a non-diffusion area remains between the P and N layers. That is, an area with a low concentration remains in a substrate. Accordingly, in this structure, the maximum width of a first or second diffusion area is larger than the thickness of a single epitaxial growth layer. Thus, this patent fails to form a fine structure in a substrate planar direction and thus does not serve to reduce the on resistance.
The structure shown in FIG. 34 is formed as follows: First, a P type impurity diffusion area is formed in a first epitaxial growth layer formed on the first semiconductor substrate. Then, a P type impurity diffusion area is formed in a second epitaxial growth layer formed on the first epitaxial growth layer. This step is repeated for about five to seven layers. Then, the P type impurities in the epitaxial growth layers are thermally diffused and thus connected together in a depth direction to form the first P base area 103. At this time, adjacent P impurity diffusion areas must be formed at a specified distance so as not to be joined together.
A MISFET having the structure shown in FIG. 34 allows the concentration of impurities to be increased by reducing the widths of the P and N type pillar layers. This enables the on resistance to be further reduced. However, to reduce the widths of the pillar layers, it is necessary to join the impurity diffusion areas 102 together lengthwise with a small amount of diffusion. As a result, the number of epitaxial growth layers (102a to 102k) increases as shown in FIG. 35, thus increasing manufacturing costs.
Further, the manufacturing costs can be cut down by reducing the number of epitaxial growth layers. However, in this case, the diffusion areas 120 must be enlarged as shown in FIG. 36. Thus, the width of the pillar layers increases, and the concentration of impurities decreases. This may degrade the on resistance.
The present invention is provided in view of these circumstances. It is an object of the present invention to provide a semiconductor device having a drift area structure with a reduced pitch between each area (P type area) exhibiting the same polarity as that of a P type and a corresponding area (N type area) exhibiting the same polarity as that of an N type and terminal area structure, in order to form MISFET elements having a fine structure and achieve complete depletion.